Content addressable memory (CAM) devices, sometimes referred to as “associative memories,” can receive a compare data value (sometimes referred to as a comparand or search key), and compare such a value against a number of stored data values. In most configurations, such an operation can match a compare data value against a very larger number of stored data values (e.g., thousands or millions), essentially simultaneously.
Such rapid compare functions have resulted in CAM devices enjoying wide application in various packet processing hardware devices, such as routers and network switches, to name just two. In a typical packet processing operation, a device can receive a packet. The packet can include a “header” having various data fields that indicate how the packet should be processed. The hardware device can utilize a matching function, provided by a CAM device, to compare one or more header fields to stored data values that can indicate how the packet is to be processed.
CAM devices are typically manufactured in integrated circuit form, as stand alone memory devices, or as some portion of an integrated circuit providing other functions.
Many CAM device configurations can include a number of CAM memory cells arranged in a logical fashion (e.g., rows, words, etc.) to store data values for comparison with a search key. Such CAM memory cells typically include a storage circuit for storing one or more bit values as well as a compare circuit for comparing the stored data value(s) with corresponding portions of a received search key.
To better understand various aspects of the present invention, a known CAM device circuit will briefly be described.
Referring now to FIG. 13, an example of a CAM device circuit is shown in a block schematic diagram and designated by the general reference character 1300. A circuit 1300 can include a match line 1302, a precharge circuit 1304 and a discharge node 1306. FIG. 13 also shows circuits equivalent to CAM cells situated in parallel with one another between match line 1302 and discharge node 1306. In the example shown, such equivalent circuits can include two n-channel metal-oxide-semiconductor (MOS) transistors having source-drain paths arranged in series with one another. It is understood that each equivalent circuit can represent all or a portion of (i.e., a leg) of a compare “stack” within a CAM cell.
A match line 1302 can provide a match indication in a compare operation. In particular, a match line 1302 can be precharged to a high power supply voltage VDD by precharge circuit 1304. In the event received compare data values are determined not to match data values stored in corresponding CAM cells, one or more CAM cells can provide a low impedance path between match line 1302 and discharge node 1306. In contrast, in the event received compare data values are determined to match data values stored in corresponding CAM cells, the CAM cells can all maintain high impedance paths between match line 1302 and discharge node 1306, maintaining match line 1302 at the precharged level.
In FIG. 13, precharge circuit 1304 can include an “AC” precharge p-channel MOS (PMOS) transistor P130 and a “DC” precharge PMOS transistor P132. Transistor P130 can have source-drain path connected between a high power supply voltage VDD and match line 1302, and a gate connected to receive precharge signal /PC. Precharge signal /PC can be activated (go low in this example) prior to a compare operation. This can ensure a match line 1302 is at a precharge level prior to the application of compare data. DC precharge transistor P132 can have source-drain path connected between a high power supply voltage VDD and match line 1302, in parallel with that of transistor P130, and can have a gate connected to a low power supply voltage VSS. In this arrangement, transistor P132 can be an “always on” transistor.
While CAM cells would ideally provide complete electrical isolation between a match line 1302 and discharge node 1306 in all but the mismatch case, in most cases a compare stack for each CAM cell can draw some amount of leakage current. Leakage currents for CAM cells are thus shown in FIG. 13 as Ieff0 to Ieffn. In such an arrangement, it is understood that CAM cells can draw a total leakage current that is the sum of Ieff0 to Ieffn, or a saturation current of DC precharge transistor P132.
U.S. Pat. No. 6,804,133 issued to Sandeep Khanna on Oct. 12, 2004 shows, among other matters, a match line control circuit that can adjust the charge current for a match in response to a valid bit and a pre-charge signal.